Bio

Dr. Aysu received his B.S degree in microelectronics engineering with a mathematics minor and his M.S degree in electrical engineering from Sabanci University, Istanbul, Turkey. He received his Ph.D. degree in computer engineering from Virginia Tech and was a post-doctoral researcher at the University of Texas at Austin before he joined NC State. Dr. Aysu conducts research on cybersecurity with an emphasis on hardware-based security. The focus of his research is the development of secure systems that prevent advanced cyber attacks targeting hardware vulnerabilities. To that end, his research interests cover applied cryptography, computer architecture, and digital hardware design. He also works on cybersecurity education and the societal impacts of cybersecurity.

Area(s) of Expertise

Computer Architecture and Systems

Publications

• A Comparison of Unified Multiplier Designs for the Falcon Post-quantum Digital Signature , Lecture Notes in Computer Science (2026)
• ASIC Tape-Out of the First Side-Channel Protected Neural Network Design , IEEE Design and Test (2026)
• Preemption-Enhanced Benchmark Suite for FPGAs , IEEE Access (2026)
• CRAFT: Characterizing and Root-Causing Fault Injection Threats at Pre-Silicon , (2025)
• Craft: Characterizing and root-causing fault injection threats at pre-silicon , arXiv preprint arXiv:2503.03877 (2025)
• EPOCH: Enabling Preemption Operation for Context Saving in Heterogeneous FPGA Systems , ArXiv.org (2025)
• Exploiting Power Side-Channel Vulnerabilities in XGBoost Accelerator , 2025 62nd ACM/IEEE Design Automation Conference (DAC) (2025)
• GateBleed: Exploiting On-Core Accelerator Power Gating for High Performance and Stealthy Attacks on AI , Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture (2025)
• Hardware-Enabled Mechanisms for Verifying Responsible AI Development , SuperIntelligence - Robotics - Safety & Alignment (2025)
• Hardware-Enabled Mechanisms for Verifying Responsible AI Development , arXiv preprint arXiv:2505.03742 (2025)

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